Inverter Compatibility｜Joint operation prove-out

Compatibility is not just plugging in — it is coordinated operation across all states

We verify DC window, pre-charge, contactor timing, power boundaries, communication, fault response and joint thermal derating between battery and target PCS/inverter.

Test project card TC-INV-26-051 Demo data

System V: 1331 V demo
PCS: 1.25 MW demo
Pass rate: 84% scenarios
Open: 2 conditional

View interface baseline Download compatibility checklist

Four compatibility capabilities · baseline checklist · three-domain ownership

What must be proven — and who owns each boundary — before claiming joint operation Demo data · COMP-B2.1

DC voltage matching Window covers SOC × T cube
Startup handshake Pre-charge to loaded ACK
Power & regulation SOP aligned with PCS map
Fault logic sync Mapped trips → safe state

Baseline checklist COMP-B2.1

Item	Scope	Owner	Status
Voltage / current / power bounds	Electrical envelope	Battery + PCS	PASS
Handshake logic	Start / run / sleep	Battery + PCS	PASS
Protection & isolation	Trip → safe state	Battery + PCS + EMS	PASS
Comm ICD freeze	CAN / Modbus	All parties	PASS
Thermal derate joint	T × SOC × P	Battery + PCS	COND
Firmware consistency	Version freeze	All parties	REVIEW
Fault recovery path	Latch / clear	Battery + PCS	PASS
Evidence pack	Report package	Program	IN PROG

Three-domain responsibility

BMS / Battery Cell limits · SOC · insulation · contactor authority
PCS / Inverter DC port · internal protection · AC status
EMS / System Dispatch · system safety · logs · override

Owns
Negotiate
Authorize

OCV @ 25 °C Baseline
OCV @ 0 / 45 °C Envelope
PCS window 600–900 V demo
Derate band Edge SOC

OCV–SOC multi-temp overlay (HTML spark · demo)

Alignment results

Check	Battery	PCS	Result
Max DC	900 V demo	900 V	PASS
Min DC	600 V demo	600 V	PASS
OVP margin	≥ 20 V	Trip 920 V	PASS
UVP margin	≥ 20 V	Trip 580 V	PASS
Derate SOC	5–95%	Matched	COND

Overall DC window · PASS (demo) — two conditional edge cases tracked

Power boundary & DC electrical interface (SLD)

Charge/discharge vs SOC, worst-case table, and DC single-line Demo data

Power vs SOC (demo)

Charge / discharge SOP overlay · HTML spark

Worst-case operating points

Case	SOC	T	P limit	Note
Cold charge	20%	0 °C	0.4C	PCS derate
Hot discharge	80%	45 °C	0.8C	Joint thermal
Low V edge	10%	25 °C	0.5C	UVP margin
High V edge	95%	25 °C	0.3C	OVP margin

DC SLD (excerpt)

Main contactor Positive / negative
Pre-charge R · timer · ACK
Fuse / breaker Coordination demo
PCS DC port 600–900 V window
Sense / HVIL Interlock chain

Startup & state handshake sequence

Eleven steps from power-up to soft recovery · with timeout / ACK rules Demo data

Power up LV / HV ready
Self-check BMS / PCS
Comm link ICD alive
Pre-charge R path
Main close Contactor ACK
Standby Ready flag
Enable EMS / local
Ramp P within SOP
Run Steady
Fault path Trip map
Soft recover Clear · re-HS

Timeout / ACK rules

Pre-charge ACK ≤ 3 s demo or abort to safe open
Main contactor feedback required before Enable
Comm loss → hold last then safe stop per ICD
Soft recover only after latch clear + role gate

Charge

Command source: EMS / local
Permit: BMS SOP · PCS ready
Limit: Min(SOP, PCS map)
Feedback: I / P / state
Safe state: Standby on trip

Discharge

Command source: EMS / local
Permit: BMS SOP · grid OK
Limit: Min(SOP, PCS map)
Feedback: I / P / AC status
Safe state: Island inhibit

Standby

Command source: Auto / EMS
Permit: HV closed · no fault
Limit: P ≈ 0
Feedback: Ready / sleep
Safe state: Open on ESTOP

Derate · fault isolate

Command source: Protection / thermal
Permit: Latch rules
Limit: Floor / zero
Feedback: Fault word
Safe state: Isolate · log

Power dynamics & fault logic verification

Dynamic response metrics plus fault event → detect → act → recover Demo data

Dynamic response (demo)

Step P settle ≤ 200 ms
Overshoot ≤ 5% demo
Ramp rate ICD limited
Comm lag ≤ 50 ms

Multi-trace power response (HTML spark)

Fault causality

Event	Detect	Action	Recover
DC OV	≤ 20 ms	Trip DC · open	Clear + re-HS
OC	≤ 50 ms	PCS stop	Latch gated
Comm loss	3× HB	Hold → stop	Re-link
Thermal	Derate map	Floor P	Cool + clear

Thermal co-derating & cross-model matrix

Joint T×SOC power ceiling and A/B/C/N model compatibility Demo data

Joint power ceiling

Temperature × SOC heatmap abstract (HTML cells · demo)

OKOKDERLIM

OKOKOKDER

DEROKOKOK

LIMDEROKOK

Cross-model matrix

Model	DC window	Handshake	Fault map	Thermal	Status
Type A	PASS	PASS	PASS	PASS	PASS
Type B	PASS	PASS	COND	PASS	COND
Type C	PASS	PLAN	PLAN	PASS	PLAN
Type N	REVIEW	PASS	PASS	COND	REVIEW

Compatibility verification ladder — nine stages

From simulation to endurance — target / evidence / result Demo data

Simulation Envelope Model pack PASS
Protocol ICD Dict / HS PASS
HIL Timing HIL log PASS
Bench DC / P Scope PASS
Integration E2E Case set 94%
Full power Rated Curve PASS
Fault inject Map Trip film PASS
Thermal Derate T log COND
Endurance Cycle Report PLAN

Boundary tests · version change · delivery pack

Three equal cards — evidence first; optional weak contact link (not a Freeze CTA) Demo data · not a full-width CTA

Boundary special tests

Test	Result	Note
Low-V discharge	PASS	UVP margin
High-V charge	PASS	OVP margin
Cold start	COND	Pre-charge time
Comm drop	PASS	Safe stop

Version change & regression

Delta logged ICD / FW IDs
Impact HS · trip · derate
Retest set Core cases
Sign-off Rev bump

Compatibility report pack

Envelope report DC / P
Handshake log Timing
Fault map Cause→act
Thermal matrix T×SOC
HIL / bench Evidence
Open items COND list

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